`timescale 1ns / 1ps
//////////////////////////////////////////////////////////////////////////////////
// Company: 
// Engineer: 
// 
// Create Date:    12:34:27 12/01/2020 
// Design Name: 
// Module Name:    EX_MEM 
// Project Name: 
// Target Devices: 
// Tool versions: 
// Description: 
//
// Dependencies: 
//
// Revision: 
// Revision 0.01 - File Created
// Additional Comments: 
//
//////////////////////////////////////////////////////////////////////////////////
module EX_MEM(
    input clk,
    input reset,
    input [31:0] instructionIn,
	 input [31:0] PCIn,
    input [31:0] resultIn,
    input [31:0] RD2In,
	 input zeroIn,
    output reg [31:0] instructionOut,
	 output reg [31:0] PCOut,
    output reg [31:0] resultOut,
    output reg [31:0] RD2Out,
	 output reg zeroOut
    );
	always @(posedge clk)
	begin
		if(reset)begin
			instructionOut <= 0;
			PCOut <= 0;
			resultOut <= 0;
			RD2Out <= 0;
			zeroOut <= 0;
		end
		else begin
			instructionOut <= instructionIn;
			PCOut <= PCIn;
			resultOut <= resultIn;
			RD2Out <= RD2In;
			zeroOut <= zeroIn;
		end
	end

endmodule
